1. Field of the Invention
The present invention relates to BiCMOS processes forming bipolar and CMOS devices on the same wafer under common processing steps, and more particularly to forming isolated NMOS transistors thereon.
2. Background Information
An isolated NMOS transistor is a common electronic semiconductor device found in many product applications and made by a number of fabricators. The P-well of an isolated NMOS is electrically and spatially separated from the P-type substrate by a continuous N-type doping region below and around it, while in contrast the standard NMOS is built within a P-well that is electrically and physically connected to the P-type substrate. Please note that this application does not pertain to any structure or method of making an isolated device using silicon on insulator (SOI) or other similar buried insulator techniques, but is restricted to standard bulk silicon BiCMOS applications.
Isolated NMOS transistors have been constructed in a number of patented ways, some of which are discussed below. These known isolated devices, using BiCMOS processes and structures, use a normal P-well region over a dedicated N-type buried layer that is connected to the surface by a vertical N-type sink. Together, these complete electrical isolation of the P-well by forming an unbroken “bucket” of N-type doping. By dedicated, it is meant that the buried N-type layer is used only for the purpose of P-well isolation and is not incorporated in the other CMOS or bipolar devices on the wafer. This NMOS isolation scheme requires at least one additional mask and associated processing steps, and thus inherently increases fabrication time and costs, and reduces yields and reliability.
The N-type buried layer for an isolated NMOS transistor is often set deep enough to allow entire P-well region to fit above it. By keeping most of the normal P-well intact, including the P-type buried layer, high breakdown voltages and low parasitic transistor gains can be achieved for the isolated NMOS device. The parasitic NPN transistor from the source or drain contact (N-type emitter), through the isolated P-well (P-type base), to the isolation layer (N-type collector) has low gain because of the large base doping and base width. The punch through breakdown between the isolated NMOS P-well and the substrate is large because the N-type isolation layer and isolation sidewalls are made thick and highly doped. The diode between the N-type isolation layer and sidewalls and the substrate can be neutralized by biasing the N-type regions high and grounding the substrate.
U.S. Pat. No. 5,075,752 ('752) to Takeo Maeda et al. describes a common BiCMOS isolated NMOS transistor used as part of a memory cell. FIG. 2J at location R1 shows an isolated NMOS device with a P-type substrate 10, an n-type tub 1, a P-type buried layer 9, P-type layer 16 with N-type collector and drain, 31 and 32. Notice that the N-type tub 1 is formed specifically for the device being made at the location R1 and is not found in the other devices. Also, notice that there is no disclosure of an isolated NMOS transistor constructed in any other fashion except with the special N-type tub.
U.S. Pat. No. 5,394,007 to Reuss et al. describes an isolated well BiCMOS structure that will accommodate an isolated NMOS transistor. However, there are additional buried layers that require extra masks and processing steps, and, so, this patent has similar limitations to the '752 patent.
Other structures that will accommodate BiCMOS isolated NMOS transistors are found in U.S. Pat. Nos. 5,348,907, 5,374,840, 5,731,619, 5,789,286, 5,859,457, and 6,033,946. All of these patents, including those in the two preceding paragraphs are hereby incorporated herein by reference. Each of these patents describes process flows that require dedicated masks and processing steps for the isolated NMOS devices. One reason to use these additional steps and masks is ability to design the NMOS isolation independent of the other, routine electronic devices. This allows the reduction of the parasitic effects and breakdowns, as previously discussed. But, at the same time, there would be the advantage of reduced fabrication costs and process complexity if the isolated NMOS device could be build with the standard process flow.